PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 226
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 2: XIO Pin Multiplexing
PNX17XX_SER_1
Preliminary data sheet
Signals
GNT_B#
GNT#
AD[31:24]
AD[23:16]
AD[15]
AD[14]
AD[13:11]
AD[10]
AD[9]
AD[8]
AD[7:2]
AD[1]
AD[0]
CBE3#
CBE2#
CBE1#
CBE0#
XIO Signals
XIO_A[25]
XIO_ACK
XIO_SEL0,1,
2,3,4
XIO_DAT[15:8]
GPIO Signals
INTREQ is an input for IDE style XIO. It may be connected to any available GPIO. This signal is then routed to the TM5250
VIC interrupt controller. Or any of the direct interrupt lines can be used. See interrupt assignments in
page
3-12.
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
O
I/O
3.1.1 NAND-Flash Interface Operation
68360
16-Bit
NA
NA
D[7:0]
A[23:16]
A[15]
A[14]
A[13:11]
A[10]
A[9]
A[8]
A[7:2]
A[1]
A[0]
A[24]
AS
R/WN
DS
A[25]
NA
CS
D[15:8]
Interfacing to a NAND-Flash involves both hardware setup and software support. The
hardware support is designed to be very flexible in supporting the standard devices
plus extensions that may be provided by some flash vendors.
recommended settings for the hardware configured for various NAND-Flash
operations.
A NAND transaction may consist of 0, 1, or 2 command phases and 0, 1, 2, 3 or 4
address phases, and n data phases. The sequence is as follows: first command, low
address (address bits [7:0]), middle address (address bits [16:8]), high address
…Continued
68360
8-Bit
NA
NA
D[7:0]
A[23:16]
A[15]
A[14]
A[13:11]
A[10]
A[9]
A[8]
A[7:2]
A[1]
A[0]
A[24]
AS
R/WN
DS
A[25]
NA
CS
NA
NOR
flash
16-Bit
NA
NA
D[7:0]
A[23:16]
A[15]
A[14]
A[13:11]
A[10]
A[9]
A[8]
A[7:2]
A[1]
A[0]
A[24]
OEN
WN
NA
A[25]
R/BN
CE
D[15:8]
Rev. 1 — 17 March 2006
NOR
Flash
8-Bit
NA
NA
D[7:0]
A[23:16]
A[15]
A[14]
A[13:11]
A[10]
A[9]
A[8]
A[7:2]
A[1]
A[0]
A[24]
OEN
WN
NA
A[25]
R/BN
CE
NA
NAND-flash
16-Bit
NA
NA
AD[7:0]
D[15:8]
NA
NA
NA
NA
NA
NA
NA
ALE
CLE
NA
REN
WEN
NA
NA
R/BN
CE
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
NAND-Flash
8-Bit
NA
NA
AD[7:0]
NA
NA
NA
NA
NA
NA
NA
NA
ALE
CLE
NA
REN
WEN
NA
NA
R/BN
CE
NA
Chapter 7: PCI-XIO Module
PNX17xx Series
Table 3
Section 6.1 on
shows
IDE
NA
NA
D[7:0]
D[15:8]
CS1
CS0
A[2:0]
DIOW
DIOR
DATA_DIR
NA
NA
IORDY
NA
NA
NA
NA
NA
NA
CE
NA
7-5
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