PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 718
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 7:
MMIO cmd.
MMIO write data
Descriptor read cmd.
Descriptor read data
Descriptor read last
Data read command
Data read data
Data read last
MII transmit data
Write status cmd.
Status write data
Write status last
Write status tag
Status write tag ack.
Tx(Rt)ProduceIndex
Tx(Rt)ConsumeIndex
Transmit example waves
0
5.5 Receive process
Issue descriptor read and
status write commands
MMIO write produce index 3
Figure 7
for this example.
Each byte transferred from memory is transmitted across the MII Interface as a byte,
and the MII interface hardware adds the preamble, frame delimiter leader, and the
CRC trailer, if hardware CRC is enabled. Once transmission on the MII Interface
commences, the transmission cannot be interrupted without generating an underrun
error, which is why descriptors and data read commands are issued as soon as
possible and are pipelined. In 10Mb/s and 100Mb/s mode, the output signals look
similar, but in 10Mb/s mode, the transmit clock is scaled down by a factor 10.
In case an RMII PHY is connected, the data communication between the MII
Interface and the PHY is communicated at half the data-width and twice the clock
frequency (50 MHz). In
doubled in the 100Mb/s mode. In 10Mb/s mode, data will only be transmitted once
every 10 clock cycles (an clock gate disables the 50MHz clock for the intervening nine
cycles).
This section outlines the receive process including the activities in the device driver
software.
Issue data read
Issue data
returned
Descriptor read data returned
Start transmission
depicts the memory transactions and the transactions on the MII interface
Preamble
Rev. 1 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
Figure
0
Write first
fragment status
Tag status
7, the frequency of the MII transmit data signal will be
3
Wait for tag acknowledge
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Update
consume
register
1
CRC
End transmission
2
3
23-45
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