PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 781
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.1 Arbiter Features
2.2 ID Mapping
After reset, the Arbiter is in “boot” mode and guarantees that each requesting agent is
given a “grant” to main memory (Round Robin is the default arbitration method).
The
The first column shows the IDs when programing the TDMA wheel. The second
column indicates which ID number to use when programing the priority and
roundrobin list.
modules. If not otherwise noted the amount of buffering per DMA channel is 256
bytes.
Table 1: Peripheral ID and Sub-Arbitration
TDMA
ID
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x0
0x1
0x2
•
•
•
•
Time-Division Multiple Access (TDMA) arbitration
–
–
Priority arbitration
–
–
Two level Round Robin arbitration
–
–
–
Dynamic arbitration scheme
–
Table 1
guarantees maximum allowed latency
128 TDMA slots
guarantees minimum required bandwidth
16 Priority slots
provides equal opportunities to the lower priority “best effort” or DMA write
agents
16 round robin slots in the first level
8 round robin slots in the second level
Two sets of arbitration parameters can be defined. Selection can be made
dynamically via software based on system needs.
ID
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
shows the mapping of each module to an unique identification numbers.
Table 1
Rev. 1 — 17 March 2006
Modules
2DDE
PCI
QVCP
VIP
VLD
FGPI
Reserved
MBS (r)
MBS (w)
10/100 MAC
FGPO
also shows the amount of sub-arbitration for the given
DMA
Channels
1 x R, 1 x W
2 x R, 2 x W
4 x R
3 x W
1 x R, 2 x W
2 x W
3 x R
3 x W
2 R x 3 W
2 x R
Buffer size
2 x 256-byte buffer
4 x 256-byte buffer
4 x 512-byte buffer
3 x 256-byte buffer
3 x 256-byte buffer
2 x 512-byte buffer
3 x 256-byte buffer
3 x 256-byte buffer
10 x 32-byte buffer
4 x 256-byte buffer
1 x 16-byte buffer
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 26: Memory Arbiter
PNX17xx Series
Transaction
size
128 Bytes
128 Bytes
128 Bytes
128 Bytes
128 Bytes
128 Bytes
128 Bytes
128 Bytes
32 Bytes
128 Bytes
26-2
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