PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 144
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 1:
RESET_IN_N
POR_IN_N
Reset Module Block Diagram
2.1 RESET_IN_N or POR_IN_N?
Reset module
Watch Dog Timer
Interrupt Counter
Figure 1
PNX17xx Series system.
POR_IN_N is meant to be used at power up of the system. By asserting this pin low
as soon as the power sequencing starts ensures limited (if not none) contentions
inside the PNX17xx Series system as well as the PNX17xx Series pin level.
Furthermore by resetting the JTAG state machine the POR_IN_N signal ensures the
PNX17xx Series pins start with the correct mode. This is the cold reset and must
always be connected.
RESET_IN_N is complementary to the POR_IN_N signal and could be referenced as
the warm reset. A typical application where the feature can be used is a system board
where the JTAG boundary scan is to be used to reset PNX17xx Series without
executing a full power down and up sequence. In this case the PNX17xx Series JTAG
state machine should not be reset. Since all PNX17xx Series pins can become
outputs in boundary scan mode it is possible to assert a 0 on the RESET_IN_N pin
while the PNX17xx Series system is still under the control of the internal JTAG state
machine. This pin may not be connected at board level.
RST_CAUSE
Bus Interface
RST_CTL
Registers
shows an overview of the Reset module connections to the remaining of the
sys_rst_out_n
(to off-chip
devices)
Rev. 1 — 17 March 2006
peri_rst_n
DCS Bus
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Test block
TM5250
int_rst_n
Module 2
Module N
Module 1
int_rst1_n
int_rst2_n
int_rst_n
int_rst_n
jtag_rst_n
PNX17xx Series
Chapter 4: Reset
4-3
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