PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 92
PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 4: TM5250 Characteristics
6. MPEG Decoding
PNX17XX_SER_1
Preliminary data sheet
TM5250 VLIW CPU Features
ISA
Instructions
Data types
Functional units
Caches
Cache policies
Line size
MMU
Protection
Multipliers
Debug
Register file
Interrupts
Timers
System Interface
Software
Development
Environment
Application Software
Architecture
PNX1300 Series, with 32-bit RISC style load/store/compute instruction set and an extensive set of
8-, 16-bit SIMD multimedia instructions
5 RISC or SIMD instructions every clock cycle
boolean, 8-, 16- and 32-bit signed and unsigned integer, 32-bit IEEE floats
4 CONST, 4 Integer FAST ALU’s, 3 ALU’s, 3 multi-bit SHIFTERs, 3 DSPALU’s, 2 DSPMUL, 2
IFMUL, 2 FALU, 1 FCOMP, 1 FTOUGH (divide, sqrt) 3 BRANCH, 1 LD/ST
64 KB 8-way set associative Level 1 ICache
16 KB 4-way set associative Level 1 Dcache
128 KB 8-way set associative Level 2 Dcache
critical word first refill, write-back, write-allocate, automatic heuristic hardware prefetch
64 bytes L1 DCache
128 bytes for the ICache and the L2 DCache
none, virtual = physical, full 4 GB space supported
Base, limit style protection, where CPU can be set to only use part of system DRAM, and hardware
ensures no references take place outside this range
up to 2 32x32-bit integer multiplies per clock
up to 2 32-bit IEEE floating point multiplies per clock
up to 4 16x16-bit multiply-adds per clock
up to 8 8x8-bit multiplies per clock
JTAG based software debugger, including hardware breakpoints for instruction and data addresses
128 entry 32-bit register file
64 auto-vectoring interrupts, with 8 programmable priority levels
Eight 32-bit timers/counters are provided. A wide selection of sources allows them to be used for
performance analysis, real-time interrupt generation and/or system event counting
The TM5250 runs asynchronously with respect to system DRAM, and can operate at a frequency
lower than system DRAM to save power, or higher than system DRAM to gain performance
The TM5250 is supported by advanced C/C++ compiler tools
Applications use the TSSA, Trimedia Streaming Software Architecture, allowing modular
development of audio, video processing functions
Debug of software running on TM5250 is performed using an interactive source
debugger with a PC JTAG plug-in board. The PC talks to the TM5250 through the
PNX17xx Series JTAG pins. The TMDBG module provides an improved version of
the PNX1300 Series JTAG debug port. The PNX17xx Series is in standalone mode.
TM5250 media processor features are presented bellow.
The TM5250 processes the audio, video and the stream de-multiplexing via software.
The Variable Length decoding as well as the authentication and the de-scrambling
are supported by two coprocessors.
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 2: Overview
2-11
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