PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 780

• Manufacturer Part Number: PNX1702EH/G,557
• Description: IC MEDIA PROC 500MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1702EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 208K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.33 V ~ 1.47 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-HBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935281647557; PNX1702EH/G; PNX1702EH/G

1. Introduction
2. Functional Description
1.1 Features
All the memory traffic of PNX17xx Series modules is centralized into an internal Hub,
through the MTL bus, before it gets to the main memory interface module. In addition
to this network function, the HUB includes a generic arbiter for memory bandwidth
allocation.
Remark: The arbiter only deals with module memory traffic and not with CPU memory
traffic which is handled by the Main Memory Interface module, see
Controller. This is different approach than the PNX1300 Series arbiter.
The key features of the HUB are:
The Arbiter module is used as an arbiter between different DMA channel clusters.
Inside these clusters traffic from related DMA channels of Peripherals are combined
by applying round-robin arbitration. (see
arbitrated DMA channels).
The arbitration engine combines Time-Division Multiple Access (TDMA), priority, and
round-robin methods; resulting in a guaranteed and high-level quality of service. The
arbitration engine ensures programmable maximum latency and programmable
minimal bandwidth to the unified resource. It also makes sure that best effort agents
are fairly granted when higher priority agents do not request the channel.
The priority table can be dynamically altered by software. Two priority tables are
implemented from which the inactive table can be changed on-the-fly. The Arbiter
hardware takes care of smooth switching between the two tables.
•
•
•
•
Chapter 26: Memory Arbiter
PNX17xx Series Data Book – Volume 1 of 1
Rev. 1 — 17 March 2006
Provides a hierarchical memory access network that connects module DMA
ports to a single access port of the Main Memory interface. DMA agents, i.e. the
PNX17xx Series modules are organized in clusters.
Includes simple round-robin sub-arbitration for lower levels of hierarchy
Provides sophisticated intermediate arbitration for upper levels of the network
hierarchy
Default settings allow each module to have access to the memory but may not fit
latency requirement as soon as many modules are turned on simultaneously
Table 1
for a list of clusters and sub-
Preliminary data sheet
Chapter 9 DDR