PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 154
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 1:
XTALO
XTALI
dds_tst_bypass
Clock Module Block Diagram
clk_dds_tst
(analog pad)
sel_div_tst
pll1_7_fb
oscillator
pad
en
xtal_clk
Figure 1
(DFT) have been added into the drawing and can be disregarded for functional
behavior. The signals in
functional operating mode.
Custom Analog Block (CAB)
low jitter PLL (external to CAB)
DDS
1.728 GHz
PLL2
shows a block diagram of the Clock Module. Additional Design For Test
/2
DDS0
DDS1
DDS2
DDS3
DDS4
DDS5
DDS6
DDS7
DDS8
bypass dds
clk_mem
Rev. 1 — 17 March 2006
DIVIDER
DIVIDER
PLL0
red
PLL1
slice_test_in
are for ATE purpose and are disabled in normal
MSB in DDSx_CTL
registers selects test input
on DDS
slice
tps_clocks
slice
tst_clk_mem
tst_clk_fpi
DFT LOGIC
MMIO-Interface
Control Regs
&
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
slice_test_out
ccb_si
tst_clk_enable
tst_ccb_shift
ccb_so
tst_clk
tst_cab_bypass
RESET_IN_N
5-3
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