PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 201
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
- Current page: 201 of 832
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Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX17XX_SER_1
Preliminary data sheet
Bit
31:0
Offset 0x04,7504
31:2
1
0
Offset 0x04,7508
Offset 0x04,750C
Offset 0x04,7510
25:24 Aligner_adjust_vdo_clk2
23:22 Aligner_adjust_area3
21:20 Aligner_adjust_fgpo
19:18 Aligner_adjust_qvcp
17:16 Aligner_adjust_qvcp_pix
15:14 Aligner_adjust_qvcp_out
13:12 Aligner_adjust_area7
11:10 Aligner_adjust_area6
31:26
31:5
31:0
3:0
4
Symbol
count_stretcher_bits
count_wakeup_bits
external_wakeup_enabl
e
gpio_interrupt_enable
freq_ctr_bits
freq_ctr_done
en_ctr_enable
freq_ctr_results
Reserved
CLK_WAKEUP_CTL
CLK_FREQ_CTL
CLK_COUNT_RESULTS
ALIGNER_ADJUST (RESERVED DO NOT MODIFY)
Acces
s
R/W
R/W
R/W
R/W
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W
R/W
W1
W1
R
R
R
…Continued
Value
0
0
0
0
11
10
10
10
10
10
10
10
0
1
1
-
-
Rev. 1 — 17 March 2006
Description
The count between clock stretches
The count to use to automatically wake-up the MMIO and processor
clocks. The register is a 32-bit register with the two LSB bit hard-
coded to zero. If the CLK_WAKEUP_CTL register is written with a
value of 0x0000_0008. Then the wake-up count will be set to a
count value of 8. This means that the lowest count value is 4
(0x0000_0004 written to the CLK_WAKEUP_CTL register)
Enables the use of pin GPIO[15] as a wake-up event.
Enables the use of the GPIO interrupt as an wake-up event.
The total time to count clock edges
Signifies that the count is done
selects which clock to count
0000: Disabled
0001: PLL0
0010: PLL1
0011: PLL2
0100: UNDEF
0101: UNDEF
0110: DDS2
0111: DDS3
1000: DDS4
1001: DDS5
1010: DDS6
1011: DDS7
1100: DDS8
The result of the count of the clock frequency counting.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Adjust the aligner for fgpo out (VDO_CLK2)
Note: this clock can not have latency added to it.
Adjust the aligner for the clock going to area 3
Adjust the aligner for fgpo out internal clock
Adjust the aligner for qvcp out internal clock
Adjust the aligner for qvcp pix clock
Adjust the aligner for qvcp out (VDO_CLK1)
Adjust the aligner for the clock going to area 7
Adjust the aligner for the clock going to area 6
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-50
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