PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 467
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 1:
Figure 2:
MMIO Bus
Top Level Block Diagram
DTL
Data
INITIATOR
DTL
Header
INITIATOR
FGPO Module Block Diagram
VDO Pads
32
DTL
MMIO
I/F
1.1 FGPO Overview
Figure 1
Busses within the PNX17xx Series. All external FGPO signals are registered and
routed through the Output Router module before leaving the PNX17xx Series.
Latency buffering of data and endian conversion is done in the MTL DTL Adapter. All
FGPO register access is through the MMIO DTL adapter.
Figure 2
Output Router
Clock Block
shows the top level connection of the FGPO module to the MMIO and MTL
shows the basic sections of the FGPO module.
DMA
ENGINE
32
Rev. 1 — 17 March 2006
fgpo_rec_sync
32
fgpo_buf_sync
Timestamp
FIFO
Chapter 13: FGPO: Fast General Purpose Output
32
32
Data
Output
Engine
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
8/16/32
64
fgpo_stop
fgpo_data
MTL Bus
fgpo_start
13-2
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