PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 731

• Manufacturer Part Number: PNX1702EH/G,557
• Description: IC MEDIA PROC 500MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1702EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 208K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.33 V ~ 1.47 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-HBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935281647557; PNX1702EH/G; PNX1702EH/G

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 11: QoS transmission example
TxRt descriptors
(low prio.)
Tx descriptors
(high prio.)
QoSTimeoutCnt
LAN
Tx clk cycles
0
5.9 Duplex Modes
Ph1,
Ph2,
Ph3
QoS example
Figure 11
In this example, the low-priority queue has two packets and the high priority queue
contains three packets. The QoSTimeout register is set to 70 transmit clock cycles.
Initially the LAN100 will start transmitting packets from the high-priority queue. As
soon as the QoSTimeout expires, the LAN100 will send out a single packet from the
low-priority queue, after which it continues transmitting packets from the high-priority
queue. As soon as the remaining packet in the high-priority queue has been
transmitted and the high-priority queue is empty, the LAN100 will continue
transmitting packets from the low-priority queue.
The LAN100 can operate in full-duplex and half-duplex mode. Half- or full-duplex
mode must be configured by the device driver software during initialization of the
LAN100.
For full duplex, the FullDuplex bit of the Command register must be set to 1 and the
FULL_DUPLEX bit of the MAC2 configuration register must be set to 1. For half
duplex, the same bits must be set to 0.
50
Ph1
100
shows an example of QoS transmissions.
PI1,
PI2
Ph2
Ph2,
Ph3
150
Rev. 1 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
PI1
200
Ph3
250
Ph3
300
PI2
PI2
350
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
400
450
500
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