PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 819

• Manufacturer Part Number: PNX1702EH/G,557
• Description: IC MEDIA PROC 500MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1702EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 208K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.33 V ~ 1.47 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-HBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935281647557; PNX1702EH/G; PNX1702EH/G

Philips Semiconductors
Volume 1 of 1
7. Detailed Example
PNX17XX_SER_1
Preliminary data sheet
The 32-bit PCI bus uses byte address conventions identical to the DTL interface and
MTL Memory Bus Interface: Refer to
Table 11: 32 Bit PCI Interface Byte Address
The DCS Network uses byte address conventions given in
The MTL Memory Bus uses the byte address conventions given in
With the above byte address conventions on the three sides of the bridge and the
byte address invariance rule for bridges, the swap modes can be derived. Since the
convention on the PCI bus closely matches those on the MTL Bus.
This section describes all steps involved in how a big-endian mode external CPU
(e.g., a Power Macintosh), paints an RGB-565 pixel format frame buffer in the
PNX17xx Series SDRAM and how this is displayed on the QVCP. This example
illustrates the following:
The Power Macintosh was the first platform that successfully demonstrated big-
endian operations across the PCI bus. Details of how this works can be found in the
Apple document “Designing PCI Cards and Drivers for Power MacIntosh Computers.”
Suppose that the big-endian CPU in the Power Macintosh uses a 32-bit store
operation to create two RGB565 pixels. Pixel 1, the left-most pixel, has (byte) address
“A” and pixel 2 has address “A+2.” Since these two pixels are transferred in a single
32-bit word, “A” is a multiple of 4.
The intermediate stages that the data goes through can be found in
PCI-AD[31:24]
4n+3
•
•
•
•
•
The Power Macintosh PCI bridge and its address invariance rule based swapper
The BIG-endian PCI pixel transfer
How data arrives correct in SDRAM in native RGB565 pixel format
How the QVCP takes it and displays it
How the TM32 CPU core sees the data
Rev. 1 — 17 March 2006
PCI-AD[23:16]
4n+2
Table
PCI-AD[15:8]
4n+1
11.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 29: Endian Mode
Table
PCI-AD[7:0]
4n+0
8.
Table
Figure 7
9.
29-15