PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 445

• Manufacturer Part Number: PNX1702EH/G,557
• Description: IC MEDIA PROC 500MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1702EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 208K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.33 V ~ 1.47 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-HBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935281647557; PNX1702EH/G; PNX1702EH/G

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 11: Double Buffer Mode
dma_base1
dma_base2
Capture Enable Mode
Using the cfen bits, video capture can be limited to odd or even or both fields. If both
fields are to be captured, the capture starts with the next odd field.
The status of the
mode (one-shot or continuous):
Programming hint: In a video conference application the captured image would be a
one-shot stream to the host memory. If you write
register, it is captured on the next VSYNC and
the next image, the
Address Generation
The line address is generated by loading the base address from the corresponding
register set at the beginning of each field and adding the line pitch to it at the
beginning of every new line.The lower three bits of the first three base address
registers are used as an intra-long-word offset for the left-most pixel components of
each line. The offset has to be a multiple of the number of bytes per component.
Double Buffer Mode
To avoid line tear caused by trying to display a frame at the same time that it is being
updated, a double buffer mode is available. In this double buffer mode, a second set
of DMA base addresses is available. After capturing and storing one complete frame
in the location described by one set, the other set is used for the next frame. The idea
is illustrated in
•
•
If osm =0, the corresponding incoming video stream is captured continuously. For
example, in a video conference application the vanity image would be a
continuous stream to the frame buffer.
If osm =1, the corresponding incoming video stream is captured one field or frame
at a time (depending on the cfen bits).
Frame 1
Figure
Even
Odd
osm
Rev. 1 — 17 March 2006
cfen and osm
(one-shot) bit in the mode-control-register specifies the capture
11.
dma_base3
dma_base4
bits must be reprogrammed.
Frame 2
cfen
Chapter 12: Video Input Processor
Even
Odd
osm
bits are cleared to 0. To capture
=1 and select field/frame in the
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
12-14