PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 164

• Manufacturer Part Number: PNX1702EH/G,557
• Description: IC MEDIA PROC 500MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1702EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 208K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.33 V ~ 1.47 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-HBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935281647557; PNX1702EH/G; PNX1702EH/G

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 3:
CAB
Block Diagram of the Clock Control Logic
2.3 Clock Control Logic
re-program PLL
parameters or
1.728 GHz PLL
divider
BLOCKING
Logic
All the generated PNX17xx Series clocks follow the generic block diagram presented
in
functional operating mode.
The clock module allows several clock sources per clock signal. The different clock
sources are selected with a multiplexer. In order to guaranty a glitch free dynamic
clock switch a blocking block is added after the clock multiplexer.
The same blocking mechanism is necessary when the PLL control register is re-
programmed since the PLL clock needs first to be stable, i.e. locks, before it can be
used by any module. So the PLL clock is first blocked by the blocking circuit before
the new PLL parameters are passed to the PLL. The Blocking circuit will block the
clock output when the turn_off signal is set by the blocking logic. The clock is blocked
after a falling edge to ensure the clock is held low. Once the blocking circuit has
blocked the clock, the turn_off_ack signal is set to high, and it is then safe to pass the
new parameters to the PLL.
Figure
clk_out
3. The signals in
“second_clk”
ext_clk
/n
n = 2,3,4,5,6
xtal_clk
Rev. 1 — 17 March 2006
clock divider
re-program
red
are for ATE purpose and are disabled in normal
BLOCKING
Logic
exit_reset reg is set
or testmode
switch mux if:
tst_clk_x
tst_clk_sel
CLOCK CONTROL LOGIC SLICE
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
clock_out
slice_tst_out
5-13