PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 342
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 8: Register Summary
Table 9: Register Description
PNX17XX_SER_1
Preliminary data sheet
Offset
0x06 51C0
0x06 51C4
0x06 5200
0x06 5204
0x06 5208
0x06 520C
0x06 5240
0x06 5280
0x06 5284
0x06 5288
0x06 528C
0x06 5290
0x06 0FFC
Bit
Generic Control and Status
Offset 0x06 5000
31
30
29:16
15
14
13
12:5
4
3
Symbol
HALT_STATUS
AUTO_HALT_STATUS
Unused
HALT
AUTO_HALT
WARM_START
Unused
DIS_WRITE_INT
DDR_DQS_PER_BYTE R/W
Symbol
ARB_CPU_LIMIT
ARB_CPU_RATIO
PF_MTL0_RD_VALID
PF_MTL0_WR_ACCEPT
PF_MTL1_RD_VALID
PF_MTL1_WR_ACCEPT
PF_IDLE
ERR_VALID
ERR_MTL_PORT
ERR_MTL_CMD_ADDR
ERR_MTL_CMD_READ
ERR_MTL_CMD_ID
MODULE_ID
5.2 Register Table
IP_2031_CTL
Access Value
R
R
R
R/W
R/W
R/W
R
R
0
0
-
0
0
0
-
1
0
Rev. 1 — 17 March 2006
Description
‘0’: Not in halt mode.
‘1’: Halt mode.
‘0’: Not in halt mode.
‘1’: Halt mode.
These bits should be ignored when read and written as 0s.
‘0’: Unhalt when in halt mode.
‘1’: Halt when not in halt mode.
‘0’: No automatic halt.
‘1’: Allow automatic halt.
‘1’: Perform a warm start of the controller. This will behave as a
unhalt operation. This can be used to start the DDR controller
without effecting the state of the external DDR memory.
These bits should be ignored when read, and written as 0s.
‘1’: DDR write burst cannot be interrupted by following read
command.
‘0’: A single “dqs” signal is provided for all “dq” byte lane. Output pin
MM_DQS[0] must be used for all byte lanes.
‘1’: A separate “dqs” signal is provided for every “dq” byte lane.
These strobe signals are used to register “dq” byte lanes.
Description
DDR ARBITER CPU LIMIT
DDR ARBITER CPU RATIO
DDR PERFORMANCE MTL0 READ VALID
DDR PERFORMANCE MTL0 WRITE ACCEPT
DDR PERFORMANCE MTL1 READ VALID
DDR PERFORMANCE MTL1 WRITE ACCEPT
DDR PERFORMANCE IDLE
DDR ERROR VALID
DDR ERROR MTL PORT
DDR ERROR MTL COMMAND ADDRESS
DDR ERROR MTL COMMAND READ
DDR ERROR MTL COMMAND ID
DDR MODULE ID
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX17xx Series
9-25
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