PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 398
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
4.8.1 Layer Underflow
4.8.2 Underflow Symptom
4.8.3 Underflow Recovery
4.8.4 Underflow Trouble-shooting
4.8.5 Underflow Handling
4.9 Setting QVCP for External VSYNC
Any time the layer position has reached but the small 16-pixel FIFO at the end of
every layer pipe has run out of available pixels, underflow occurs.
Should an underflow occur, the layer would fetch and dump remaining data for the
current field/frame. The next field/frame would be fetched and displayed as normal.
The underflow interrupt status would stay asserted until an interrupt-status-clear is
programmed.
Set the following bits in MMIO register 0x10,E020 as follows:
•
•
•
•
•
•
•
•
•
•
•
•
Only portion of a picture is displayed or occasional blinking of picture happens
Underflow interrupt bit is set.
Check if the DMA source width settings (0x10,Ex08) matches the initial layer
width (0x10,Ex34)
Check if the initial layer width (0x10,Ex34) matches the final layer width
(0x10,ExB4) for the non-scaled layer.
Check if the final layer width (0x10,ExB4) is within acceptable cropping range for
LINT or HSRU scaling.
Check whether the DMA start fetch (0x10,ExC8) is at line number too close to the
display position. Note that about 64 pixels is QVCP’s input-to-output latency. So,
depending on the system-memory latency, the DMA fetch should start as early as
possible, in order to make up for the request-to-data latency.
Check if the system memory arbiter is giving high priority to QVCP.
Check if QVCP demands exceed allocated memory bandwidth.
bit 1 (master) = 1;
bit 2 (Trigger_pol) = 1; for posisitive edge trigger
bit 16 (SYNCCtl) = 0; VSYNC pin becomes an input
bit 24 (VSYNCPol) = 0;
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 11: QVCP
11-41
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