PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 251
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 9: Registers Description
PNX17XX_SER_1
Preliminary data sheet
Bit
24:19
18:16
15:8
7:0
Offset 0x04 0084
31:1
1:0
Offset 0x04 0088
31:24
23:16
15:3
2
1
0
Offset 0x04 008C
31:24
20:16
11:8
7:3
2:0
Symbol
Reserved
version
Next Item Pointer
Cap_ID
Reserved
pwr_state
upper_io3_addr
upper_io2_addr
Reserved
use_io3_addr
use_io2_addr
use_pcibase2_as_io
Reserved
slv_memrd_fetch
slv_threshold
Reserved
slv_mrmul_fetch
Image of Configuration Reg 44
PCI_IO
Slave DTL tuning
Acces
s
R
R
R
R
R
R/W*
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R
R/W
Value
0
010
00
01
0
0
0
0
0
0
0
0
0
111
10
0
001
Rev. 1 — 17 March 2006
Description
Indicates compliance with version 1.1 of PM.
There are no other extended capabilities.
Indicates this is power management data structure.
Power State
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Bits [31:24] of IO address during PCI IO transactions.
Bits [23:16] of IO address during PCI IO transactions.
Use “upper_io3_addr” as the upper address for PCI IO transactions.
Use “upper_io3_addr” and “upper_io2_addr” as the upper address
for PCI IO transactions.
1: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as IO
transactions. The address will unchanged or modified with an
alternate upper addresses selected above.
0: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as
memory transactions with unchanged address.
PCI slave DTL read block size for memory read command. Default
value is 8 32-bit words. Maximum is 64 32-bit words.
Threshold (amount of data not consumed from previous read
request) for when PCI slave DTL requests more read data when
responding to memory read command. This must be set to a value
less than the smallest of slv_memrd_fetch, Cache Line Size or
read_block_siz. Default is 3 32-bit words. Maximum value is 32 32-
bit words.
Encoded PCI slave DTL read block size for memory read multiple
command
siz : read_block_siz
000:
001:
010:
011:
100: 128 bytes
101: 256 bytes
110: 512 bytes
111: 1024 bytes
16 bytes
32 bytes
64 bytes
8 bytes
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-30
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