SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1028

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

40.3.4.3
Table 40-1.
Notes:
40.3.4.4
40.3.4.5
40.3.4.6
1028
buffer of a multiple buffer
with contiguous DADDR
with contiguous SADDR
1) Single Buffer or Last
2) Multi Buffer transfer
3) Multi Buffer transfer
4) Multi Buffer transfer
with LLI support
Transfer Type
1. USR means that the register field is manually programmed by the user.
2. CONT means that address are contiguous.
3. LLI means that the register field is updated with the content of the linked list item.
transfer
SAM3U Series
Programming DMAC for Multiple Buffer Transfers
Contiguous Address Between Buffers
Suspension of Transfers Between buffers
Ending Multi-buffer Transfers
Multiple Buffers Transfer Management Table
AUTO
In this case, the address between successive buffers is selected to be a continuation from the
end of the previous buffer. Enabling the source or destination address to be contiguous between
buffers is a function of DMAC_CTRLAx.SRC_DSCR and DMAC_CTRLAx.DST_DSCR
registers.
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
Note:
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
All multi-buffer transfers must end as shown in Row 1 of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
For rows 2, 3, and 4 the user must setup the last buffer descriptor in memory such that both
LLI.DMAC_CTRLBx.SRC_DSCR and LLI.DMAC_CTRLBx.DST_DSCR are one and
LLI.DMAC_DSCRx is set to 0.
0
0
0
0
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the
• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’,
channel number.
when n is the channel number.
SRC_REP
The buffer complete interrupt is generated at the completion of the buffer transfer to the
destination.
–
–
0
–
DST_REP
–
0
–
–
SRC_DSCR
1
0
1
0
DST_DSCR
1
1
0
0
BTSIZE
Table 40-1 on page
USR
LLI
LLI
LLI
SADDR
CONT
USR
LLI
LLI
DADDR
CONT
USR
6430E–ATARM–29-Aug-11
1028. At the end of
LLI
LLI
Fields
Other
USR
LLI
LLI
LLI