SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 827

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

37.8.7
37.8.7.1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
WRITE_MULTIPLE_BLOCK
One Block per Descriptor
3. Wait for XFRDONE in HSMCI_SR register.
1. Wait until the current command execution has successfully terminated.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Program HSMCI_DMA register with the following fields:
5. Issue a WRITE_MULTIPLE_BLOCK command.
6. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set with the starting address of
e. The DMAC_DADDRx register for channel x must be word aligned.
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
h. Program DMAC_CFGx register for channel x with the following field’s values:
a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
– OFFSET field with dma_offset.
– CHKSIZE is user defined.
– DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit
block of data. Block n of data is transferred with descriptor LLI(n).
was previously set to false.
reading the DMAC_EBCISR register.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA.CHKSIZE Field.
–BTSIZE is programmed with CEILING(block_length/4).
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
–Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and
DMA Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
waiting for request.
SAM3U Series
SAM3U Series
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