SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 959

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

39.6.6
Figure 39-5. Allocation and Reorganization of the DPRAM
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
DPRAM Management
Device:
UDPHS_EPTCTLENBx.EPT_ENABL = 1
UDPHS_EPTCFGx.BK_NUMBER <> 0
Endpoints 0..5
Activated
Free Memory
EPT5
EPT4
EPT3
EPT2
EPT1
EPT0
Endpoints can only be allocated in ascending order, from the endpoint 0 to the last endpoint to
be allocated. The user shall therefore configure them in the same order.
The allocation of an endpoint x starts when the Number of Banks field in the UDPHS Endpoint
Configuration Register (UDPHS_EPTCFGx.BK_NUMBER) is different from zero. Then, the
hardware allocates a memory area in the DPRAM and inserts it between the x-1 and x+1 end-
points. The x+1 endpoint memory window slides up and its data is lost. Note that the following
endpoint memory windows (from x+2) do not slide.
Disabling an endpoint, by writing a one to the Endpoint Disable bit in the UDPHS Endpoint Con-
trol Disable Register (UDPHS_EPTCTLDISx.EPT_DISABL), does not reset its configuration:
To free its memory, the user shall write a zero to the UDPHS_EPTCFGx.BK_NUMBER field.
The x+1 endpoint memory window then slides down and its data is lost. Note that the following
endpoint memory windows (from x+2) do not slide.
Figure 39-5 on page 959
example.
• the Endpoint Banks (UDPHS_EPTCFGx.BK_NUMBER),
• the Endpoint Size (UDPHS_EPTCFGx.EPT_SIZE),
• the Endpoint Direction (UDPHS_EPTCFGx.EPT_DIR),
• and the Endpoint Type (UDPHS_EPTCFGx.EPT_TYPE).
1. The endpoints 0 to 5 are enabled, configured and allocated in ascending order. Each
2. The endpoint 3 is disabled, but its memory is kept allocated by the controller.
3. In order to free its memory, its UDPHS_EPTCFGx.BK_NUMBER field is written to zero.
4. If the user chooses to reconfigure the endpoint 3 with a larger size, the controller allo-
endpoint then owns a memory area in the DPRAM.
The endpoint 4 memory window slides down, but the endpoint 5 does not move.
cates a memory area after the endpoint 2 memory area and automatically slides up the
Device:
UDPHS_EPTCTLDIS3.EPT_DISABL = 1 UDPHS_EPTCFG3.BK_NUMBER = 0
Endpoint 3
(always allocated)
Disabled
Free Memory
EPT5
EPT4
EPT3
EPT2
EPT1
EPT0
illustrates the allocation and reorganization of the DPRAM in a typical
Device:
Memory Freed
Endpoint 3
EPT4 Lost Memory
Free Memory
EPT5
EPT4
EPT2
EPT1
EPT0
Device:
UDPHS_EPTCTLENB3.EPT_ENABL = 1
UDPHS_EPTCFG3.BK_NUMBER <> 0
EPT3 (larger size)
Endpoint 3
Activated
Free Memory
EPT4
EPT2
EPT1
EPT0
EPT5
SAM3U Series
SAM3U Series
Conflict
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