SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 433
SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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25.18.21 SMC Mode Register
Name:
Address:
Access:
Reset:
• READ_MODE
1 (NRD_CTRL): The Read operation is controlled by the NRD signal.
0 (NCS_CTRL): The Read operation is controlled by the NCS signal.
• WRITE_MODE
1 (NWE_CTRL): The Write operation is controlled by the NWE signal.
0 (NCS_CTRL): The Write operation is controller by the NCS signal.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase
Read and Write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
• Disabled: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
cycle is resumed from the point where it was stopped.
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
31
23
15
–
–
–
7
–
Value
0
1
2
3
0x400E0080 [0], 0x400E0094 [1], 0x400E00A8 [2], 0x400E00BC [3]
0x10000003
SMC_MODEx [x=0..3]
Read-write
30
22
14
–
–
–
6
–
DISABLED
FROZEN
READY
Name
29
21
13
–
–
–
5
EXNW_MODE
Description
Disabled
Reserved
Frozen Mode
Ready Mode
TDF_MODE
DBW
28
20
12
–
4
27
19
11
–
–
3
–
26
18
10
–
–
2
–
TDF_CYCLES
WRITE_MODE READ_MODE
SAM3U Series
SAM3U Series
25
17
–
9
–
1
BAT
24
16
–
8
0
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