SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1039

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SAM3U2C

Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3U2C

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
6430E–ATARM–29-Aug-11
• If you program the BTSIZE field in the DMAC_CTRLA, as zero, and the DMAC is defined as
• When hardware handshaking interface protocol is fully implemented, a peripheral is expected
• Multiple Transfers involving the same peripheral must not be programmed and enabled on
• When a Peripheral is flow controller, the targeted DMAC Channel must be enabled before the
the flow controller, then the channel is automatically disabled.
to deassert any sreq or breq signals on receiving the ack signal irrespective of the request
the ack was asserted in response to.
different channel, unless this peripheral integrates several hardware handshaking interface.
Peripheral. If you do not ensure this the DMAC Channel might miss a Last Transfer Flag, if
the First DMAC request is also the last transfer.
SAM3U Series
1039

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