SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 886

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 38-9. Method 1 (UPDM = 0)
886
886
Method 1: Manual write of duty-cycle values and manual trigger of the update
UPDULOCK
SAM3U Series
SAM3U Series
CDTYUPD
CCNT0
CDTY
0x20
0x20
In this mode, the update of the period value, the duty-cycle values and the dead-time values
must be done by writing in their respective update registers with the CPU (respectively
PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).
To trigger the update, the user must use the bit UPDULOCK of the
Update Control Register”
PWM period) the synchronous channels:
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read
0.
Sequence for Method 1:
• If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
1. Select the manual write of duty-cycle values and the manual update by setting the
2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register.
3. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
4. If an update of the period value and/or the duty-cycle values and/or the dead-time val-
5. Set UPDULOCK to 1 in PWM_SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. At this
synchronous channels.
UPDM field to 0 in the PWM_SCM register
ues is required, write registers that need to be updated (PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPDx).
moment the UPDULOCK bit is reset, go to
0x40
0x40
0x60
(PWM_SCUC) which allows to update synchronously (at the same
0x60
Step
4.) for new values.
“PWM Sync Channels
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11