SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 832

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

37.8.8.3
832
832
SAM3U Series
SAM3U Series
Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)
One DMA Transfer descriptor is used to perform the HSMCI block transfer, the DMA writes a
rounded up value to the nearest multiple of 4.
4. Enable DMADONE interrupt in the HSMCI_IER register.
5. Poll CBTC[x] bit in the DMAC_EBCISR Register.
6. If a new list of buffers shall be transferred, repeat step 7. Check and handle HSMCI
7. Poll FIFOEMPTY field in the HSMCI_SR.
8. Send The STOP_TRANSMISSION command writing HSMCI_ARG then
9. Wait for XFRDONE in HSMCI_SR register.
1. Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK.
2. Set the ROPT field to 1 in the HSMCI_DMA register.
3. Issue a READ_MULTIPLE_BLOCK command.
4. Program the DMA controller to use a list of descriptors:
q. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If
r.
s. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater
t.
errors.
HSMCI_CMDR.
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
c. Program the channel registers in the Memory with the first descriptor. This descrip-
d. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting
e. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
f.
g. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
–SRC_PER is programmed with the hardware handshaking ID of the targeted
LLI_B(n) is the last descriptor, then program LLI_B(n).DMAC_DSCR with 0.
Program DMAC_CTRLBx register for channel x with 0, its content is updated with
the LLI Fetch operation.
than 4 else with address of LLI_B(0).
Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting
address of the HSMCI_FIFO address.
Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with Ceiling(block_length/4).
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0. (descriptor fetch is enabled for the SRC)
for request.
reading the DMAC_EBCISR register.
tor will be word oriented. This descriptor is referred to as LLI_W(n), standing for LLI
word oriented transfer for block n.
HSMCI Host Controller
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11