SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1070

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

41.5.8
41.5.9
1070
SAM3U Series
Conversion Triggers
Sleep Mode and Conversion Sequencer
Conversions of the active analog channels are started with a software or a hardware trigger. The
software trigger is provided by writing the Control Register (ADC12B_CR) with the START bit at
1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM
Event lines or the external trigger input of the ADC12B (AD12BTRG). The hardware trigger is
selected with the field TRGSEL in the Mode Register (ADC12B_MR). The selected hardware
trigger is enabled with the TRGEN bit in the Mode Register (ADC12B_MR).
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at
each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a
range of 2 MCK clock periods to 1 ADC12B clock period.
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be pro-
grammed in Waveform Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The
ADC12B hardware logic automatically performs the conversions on the active channels, then
waits for a new request. The Channel Enable (ADC12B_CHER) and Channel Disable
(ADC12B_CHDR) Registers enable the analog channels to be enabled or disabled
independently.
If the ADC12B is used with a PDC, only the transfers of converted data from enabled channels
are performed and the resulting data buffers should be interpreted accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if
a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or
the software trigger.
The ADC12B Sleep Mode maximizes power saving by automatically deactivating the ADC12B
when it is not being used for conversions. Sleep Mode is selected by setting the SLEEP bit in the
Mode Register ADC12B_MR.
Two sleep Mode are selectable (OFFMODES): STANDBY Mode and OFF Mode. In Standby
Mode, the ADC12B is powered off except voltage reference to allow fast startup. In OFF Mode
the ADC12B is totally powered off.
Table 41-8.
The SLEEP mode is automatically managed by a conversion sequencer, which can automati-
cally process the conversions of all channels at lowest power consumption.
SLEEP Bit
0
1
1
Low Power Modes According SLEEP Bit and OFFMODES Bit.
OFFMODES Bit
trigger
start
_
0
1
delay
Low Power Mode
Standby Mode
Normal Mode
Off Mode
6430E–ATARM–29-Aug-11