SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1168

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

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6430B
SAM3U Series
Comments
Introduction:
Section 1. ”SAM3U
2x TWIs (SAM3U1C/2C/4C have 1), up to 5x SPIs SAM3U1C/2C/4C have 4),
Table 1-1, “Configuration Summary”
SAM3U4/3/2C rows FWUP replaces NO in FWUP,SHDN pins column.
Figure 2-1 ”144-pin SAM3U4/2/1E Block Diagram”
updated, SM cell removed; UART moved to peripheral area, added Flash Unique block, removed 12B from
ADC block, added SysTick counter and Fmax 96MHz to M3 block. FWUP replaces WKUP in fig 2-1, FWUP
added to fig 2-2.
Figure 2-2 ”100-pin SAM3U4/2/1C Block
Table 3-1, “Signal Description
details given in footnote.
VDDIN, VDDOUT added to table.
”Serial Wire/JTAG Debug Port (SWJ-DP)”
status of pulldowns and pullups specified.
Section 4. ”Package and
Section 4.1 ”SAM3U4/2/1E Package and
finalized in datasheet.
Section 5.5.1 ”Backup
Figure 5-4 ”Wake-up
Table 5-1, “Low Power Mode Configuration
“Previous state saved.”
Figure 5-3 ”Backup Batteries
Section 6.6 ”NRSTB
Section 6. ”Input/Output Lines”
Section 6.1 ”General Purpose I/O Lines (GPIO)”
Line Considerations”.
Figure 6-1 ”On-Die Termination
Section 6.8 “PIO Controllers”, removed.
Section 8. ”Product
Section 9.
Memories”
Section 9.1.3.5 ”Security Bit
Table 7-3, “SAM3U Master to Slave
Section 7.2 ”APB/AHB
Table 11-3, “Multiplexing on PIO Controller B (PIOB)”
Section 12.10.1 ”12-bit High Speed
“Quadrature Decoder Logic” on page 51
Section 12.10.1 ”12-bit High Speed
Section 12.10.2 ”10-bit Low Power
ADC12B:
Section 41.6.6 ”ADC12B Analog Control
”Memories”; now comprises
.
Description”, Updated: 52 Kbytes of SRAM. 4x USARTs (SAM3U1C/2C/4C have 3), up to
Mapping”, title changed from “Memories”.
Pin”, VDDIO changed to VDDBU
Source”, BODEN replaced by SMEN. FWUP → Falling Edge Detector.
Mode”, BOD replaced by Supply Monitor/SM.
Bridges”, reference to ADC updated “10-bit ADC, 12-bit ADC (ADC12B)”.
Pinout”; reorganized according to product.
Feature”, updated
Used”, FWUP replaces FWKUP.
List”, Schmit Trigger added
replaces Section 5.8 “Programmable I/O Lines”.
schematic”, added.
ADC”, Ksample values updated on 2nd item of list.
ADC”,
ADC”, 2nd item on list updated.
Access”, Slave 9, High Speed Peripheral Bridge line added.
EBI column updated, 8 bits for SAM3U1C/2C/4C
Section 9.1 ”Embedded Memories”
properly stated in list of TC functions.
Register”,IBCTL reasigned to fields 8 and 9
Diagram”, NWR1/NBS1, NXRP0, A0 removed from block diagram,
Pinout”,
replaced ICE and JTAG. This section of the table updated
Section 12.10.2 ”10-bit Low Power
Summary”, PIO state in Low Power Mode, backup mode is;
and
Section 4.2 ”SAM3U4/2/1C Package and
and
Section 6.2 ”System I/O Lines”
ADC12B2, ADC12B3 properly listed.
Figure 2-2 ”100-pin SAM3U4/2/1C Block Diagram”
”PIO Controller - PIOA - PIOB -
and
ADC”, titles changed.
Section 9.2 ”External
replace Section 6. “I/O
PIOC”. exception
Pinout”, pinouts
6430E–ATARM–29-Aug-11
Change
Request
Ref.
6400
6642
6482/6642
rfo/
6480
rfo
6471/rfo
6607
rfo
6645
6642
6646
6481/rfo
6663
6397
rfo
6649