SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 488

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SAM3U2C

Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3U2C

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
28.14.10 PMC Clock Generator PLLA Register
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in the
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated.
1 up to 2047 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
488
DIVA
0
1
2 - 255
31
23
15
7
SAM3U Series
CKGR_PLLAR
0x400E0428
Read-write
30
22
14
6
29
21
13
1
5
Divider Selected
Divider output is 0
Divider is bypassed (DIVA=1)
Divider output is the selected clock divided by DIVA
28
20
12
4
MULA
DIVA
“PMC Write Protect Mode
27
19
11
3
PLLACOUNT
26
18
10
2
Register”.
MULA
25
17
9
1
6430E–ATARM–29-Aug-11
24
16
8
0

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