SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 641

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 33-19. TWI Read Operation with Single Data Byte and Internal Address
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Internal address size (IADRSZ)
Read Receive Holding register
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
TWI_CR = START | STOP
Read ==> bit MREAD = 1
Set the internal address
Set the Control register:
- Device slave address
TWI_IADR = address
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
Start the transfer
- Master enable
Yes
TXCOMP = 1?
Set TWI clock
RXRDY = 1?
Yes
BEGIN
END
No
No
SAM3U Series
SAM3U Series
641
641