SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1038

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

40.3.6.1
40.4
1038
DMAC Software Requirements
SAM3U Series
Abnormal Transfer Termination
When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the
DMAC_CHSRx.SUSPEND[n] bit is high, the DMAC_CHSRx.EMPTY[n] is asserted once the
contents of the FIFO do not permit a single word of DMAC_CTRLAx.DST_WIDTH to be formed.
However, there may still be data in the channel FIFO but not enough to form a single transfer of
DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remain-
ing data in the channel FIFO are not transferred to the destination peripheral. It is permitted to
remove the channel from the suspension state by writing a ‘1’ to the DMAC_CHER.RESUME[n]
field register. The DMAC transfer completes in the normal manner. n defines the channel
number.
Note:
A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit,
DMAC_CHDR.ENABLE[n] where n is the channel number. This does not mean that the channel
is disabled immediately after the DMAC_CHSR.ENABLE[n] bit is cleared over the APB inter-
face. Consider this as a request to disable the channel. The DMAC_CHSR.ENABLE[n] must be
polled and then it must be confirmed that the channel is disabled by reading back 0.
Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Con-
figuration Register (DMAC_EN.ENABLE bit). Again, this does not mean that all channels are
disabled immediately after the DMAC_EN.ENABLE is cleared over the APB slave interface.
Consider this as a request to disable all channels. The DMAC_CHSR.ENABLE must be polled
and then it must be confirmed that all channels are disabled by reading back ‘0’.
Note:
Note:
1. If software wishes to disable a channel n prior to the DMAC transfer completion, then it
2. Software can now poll the DMAC_CHSR.EMPTY[n] bit until it indicates that the channel
3. The DMAC_CHER.ENABLE[n] bit can then be cleared by software once the channel n
• There must not be any write operation to Channel registers in an active channel after the
• You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte,
• After the software disables a channel by writing into the channel disable register, it must re-
channel enable is made HIGH. If any channel parameters must be reprogrammed, this can
only be done after disabling the DMAC channel.
half-word and word aligned address depending on the source width and destination width.
enable the channel only after it has polled a 0 in the corresponding channel enable status
register. This is because the current AHB Burst must terminate properly.
can set the DMAC_CHER.SUSPEND[n] bit to tell the DMAC to halt all transfers from
the source peripheral. Therefore, the channel FIFO receives no new data.
n FIFO is empty, where n is the channel number.
FIFO is empty, where n is the channel number.
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to
receive an acknowledgement.
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. For read sensitive
source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to
receive an acknowledgement.
6430E–ATARM–29-Aug-11