SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 820

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

37.8.4
820
820
SAM3U Series
SAM3U Series
Write Operation
In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value
when writing non-multiple block size. If the bit PADV is 0, then 0x00 value is used when padding
data, otherwise 0xFF is used.
If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer.
The following flowchart
DMA facilities. Polling or interrupt method can be used to wait for the end of write according to
the contents of the Interrupt Mask Register (HSMCI_IMR).
(Figure
37-9) shows how to write a single block with or without use of
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11