SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 963

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 39-7. NYET Example with Two Endpoint Banks
39.6.9.3
39.6.9.4
39.6.9.5
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
t = 0
data 0 ACK
Data IN
Bulk IN or Interrupt IN
Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)
Bank 1
Bank 0
t = 125 μs
E
F
Data IN packets are sent by the device during the data or the status stage of a control transfer or
during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under
the control of the application or under the control of the DMA channel.
There are three ways for an application to transfer a buffer in several packets over the USB:
The application can write one or several banks.
A simple algorithm can be used by the application to send packets regardless of the number of
banks associated to the endpoint.
Algorithm Description for Each Packet:
The application is notified that it is possible to write a new packet to the DPR by the
TX_PK_RDY interrupt. This interrupt can be enabled or masked by setting the TX_PK_RDY bit
in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
Algorithm Description to Fill Several Packets:
Using the previous algorithm, the application is interrupted for each packet. It is possible to
reduce the application overhead by writing linearly several banks at the same time. The
AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the
UDPHS_EPTCTLENBx register.
The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the interven-
tion of the CPU. This means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit)
is done by hardware.
• packet by packet (see
•
• DMA (see
• The application waits for TX_PK_RDY flag to be cleared in the UDPHS_EPTSTAx register
• The application writes one USB packet of data in the DPR through the
• The application sets TX_PK_RDY flag in the UDPHS_EPTSETSTAx register.
data 1 NYET
64
before it can perform a write access to the DPR.
memory window.
KB (see
Bank 1
Bank 0
t = 250 μs
E'
F
39.6.9.6
39.6.9.5
Bank 1
Bank 0
PING ACK
F
E
below)
below)
39.6.9.5
t = 375 μs
Bank 1
Bank 0
data 0 NYET
below)
F
E
Bank 1
Bank 0
t = 500 μs
F
F
PING NACK
Bank 1
Bank 0
E'
F
t = 625 μs
Bank 1
Bank 0
PING ACK
SAM3U Series
SAM3U Series
E
F
64
E: empty
E': begin to empty
F: full
KB endpoint logical
963
963