SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 964

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

39.6.9.6
964
964
SAM3U Series
SAM3U Series
Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
The application is notified that all banks are free, so that it is possible to write another burst of
packets by the BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the
BUSY_BANK flag in the UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism
does not operate.
A Z e r o L e n g t h P a c k e t c a n b e s e n t b y s e t t i n g j u s t t h e T X _ P K T R D Y f l a g i n t h e
UDPHS_EPTSETSTAx register.
The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buf-
fer from the memory to the DPR or from the DPR to the processor memory under the UDPHS
control. The DMA can be used for all transfer types except control transfer.
Example DMA configuration:
The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention
of the CPU. This means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is
done by hardware.
A transfer descriptor can be used. Instead of programming the register directly, a descriptor
s h o u l d b e p r o g r a m m e d a n d t h e a d d r e s s o f t h i s d e s c r i p t o r i s t h e n g i v e n t o
UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field (Load Next Descrip-
tor Now) in UDPHS_DMACONTROLx register.
The structure that defines this transfer descriptor must be aligned.
Each buffer to be transferred must be described by a DMA Transfer descriptor (see
DMA Channel Transfer Descriptor” on page
executing transfer of the buffer, the UDPHS may fetch a new transfer descriptor from the mem-
• The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The
• The application writes a number of bytes inferior to the number of free DPR banks for the
• If the last packet is incomplete (i.e., the last byte of the bank has not been written) the
1. Program UDPHS_DMAADDRESS x with the address of the buffer that should be
2. Enable the interrupt of the DMA in UDPHS_IEN
3. Program UDPHS_ DMACONTROLx:
application must wait that at least one bank is free.
endpoint. Each time the application writes the last byte of a bank, the TX_PK_RDY signal is
automatically set by the UDPHS.
application must set the TX_PK_RDY bit in the UDPHS_EPTSETSTAx register.
transferred.
– Size of buffer to send: size of the buffer to be sent to the host.
– END_B_EN: The endpoint can validate the packet (according to the values
– END_BUFFIT: generate an interrupt when the BUFF_COUNT in
– CHANN_ENB: Run and stop at end of buffer
programmed in the AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.)
(See
with
UDPHS_DMASTATUSx reaches 0.
DMA)
“UDPHS Endpoint Control Register” on page 1002
1013). Transfer descriptors are chained. Before
and
Figure 39-12. Autovalid
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
“UDPHS