SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 384

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.16 NAND Flash Controller Operations
25.16.1
25.16.2
Figure 25-31. NFC/NAND Flash Access Example
384
384
SAM3U Series
SAM3U Series
NFC Overview
NFC Control Registers
The NFC can handle automatic transfers, sending the commands and address to the NAND
Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It mini-
mizes the CPU overhead.
NAND Flash Read and NAND Flash Program operations can be performed through the NFC
Command Registers. In order to minimize CPU intervention and latency, commands are posted
in a command buffer. This buffer provides zero wait state latency. The detailed description of the
command encoding scheme is explained below.
The NFC handles automatic transfer between the external NAND Flash and the chip via the
NFC SRAM. It is done via NFC Command Registers.
The NFC Command Registers are very efficient to use. When writing to these registers:
So, in one single access the command is sent and immediately executed by the NFC. Even two
commands can be programmed within a single access (CMD1, CMD2) depending on the
VCMD2 value.
The NFC can send up to 5 Address cycles.
Figure 25-31
ory and correspondence with NFC Address Command Register.
For more details refer to
The NFC Command Registers can be found at address
Table 25-4, “External Memory
Reading the NFC command register (to any address) will give the status of the NFC. Especially
useful to know if the NFC is busy, for example.
• the address of the register (NFCADDR_CMD) contains the command used,
• the data of the register (NFCDATA_ADDT) contains the address to be sent to the NAND
Flash.
00h
Col. Add1
below shows a typical NAND Flash Page Read Command of a NAND Flash Mem-
CMD1
Column Address
Col. Add2
“NFC Address Command” on page
Depends on ACYCLE value
ADD cycles (0 to 5)
Mapping”.)
Row Add1 Row Add2 Row Add3
Row Address
If VCMD2 = 1
CMD2
386.
0x68000000 - 0x6FFFFFFF.
30h
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
(See