SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1068
SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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41.5.6
41.5.7
Figure 41-3. EOCx and DRDY Flag Behavior
1068
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
CHx
SAM3U Series
Power Consumption Adjustment
Conversion Results
Write the ADC_CR
with START = 1
The power consumption of the ADC12B can be adjusted through a 2-bit bias control (IBCTL bit
in ADC12B_ACR register) providing possibilities for smart optimization of power and effective
resolution relative to the application speed request.
Please refer to the Electrical Characteristics of the product datasheet for further details.
When a conversion is completed, the resulting 12-bit digital value is stored in the Channel Data
Register (ADC12B_CDR) of the current channel and in the ADC12B Last Converted Data Regis-
ter (ADC12B_LCDR).
The channel EOC bit in the Status Register (ADC12B_SR) is set and the DRDY bit is set. In the
case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case,
either EOC and DRDY can trigger an interrupt.
Reading one of the ADC12B_CDR registers clears the corresponding EOC bit. Reading
ADC12B_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted
channel.
Conversion Time
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Conversion Time
Read the ADC_LCDR
6430E–ATARM–29-Aug-11
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