SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 532

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SAM3U2C

Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3U2C

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
30.7.17
Name:
Address:
Access:
• P0-P31: Input Change Interrupt Status
0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
30.7.18
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• P0-P31: Multi Drive Enable.
0 = No effect.
1 = Enables Multi Drive on the I/O line.
532
532
P31
P23
P15
P31
P23
P15
P7
P7
31
23
15
31
23
15
7
7
SAM3U Series
SAM3U Series
PIO Controller Interrupt Status Register
PIO Multi-driver Enable Register
P30
P22
P14
P30
P22
P14
P6
P6
30
22
14
30
22
14
PIO_ISR
0x400E0C4C (PIOA), 0x400E0E4C (PIOB), 0x400E104C (PIOC)
Read-only
6
PIO_MDER
0x400E0C50 (PIOA), 0x400E0E50 (PIOB), 0x400E1050 (PIOC)
Write-only
6
P13
P13
P29
P21
P29
P21
P5
P5
29
21
13
29
21
13
5
5
P28
P20
P12
P28
P20
P12
P4
P4
28
20
12
28
20
12
4
4
“PIO Write Protect Mode
P11
P11
P27
P19
P27
P19
P3
P3
27
19
11
27
19
11
3
3
P26
P18
P10
P26
P18
P10
P2
P2
26
18
10
26
18
10
2
2
Register”.
P25
P17
P25
P17
P9
P1
P9
P1
25
17
25
17
9
1
9
1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
P24
P16
P24
P16
P8
P0
P8
P0
24
16
24
16
8
0
8
0

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