SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 309

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.4.2
21.4.2.1
21.4.2.2
Figure 21-2. Code Read Optimization for FWS = 0
Note:
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Buffer 0 (128bits)
Buffer 1 (128bits)
ARM Request
Data To ARM
Flash Access
Master Clock
When FWS is equal to 0, all the accesses are performed in a single-cycle access.
(32-bit)
Read Operations
128-bit or 64-bit Access Mode
Code Read Optimization
@Byte 0
XXX
XXX
Bytes 0-15
An optimized controller manages embedded Flash reads, thus increasing performance when the
processor is running in Thumb2 mode by means of the 128- or 64- bit wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
The read operations can be performed with or without wait states. Wait states must be pro-
grammed in the field FWS (Flash Read Wait State) in the Flash Mode Register (EEFC_FMR).
Defining FWS to be 0 enables the single-cycle access of the embedded Flash. Refer to the Elec-
trical Characteristics for more details.
By default the read accesses of the Flash are performed through a 128-bit wide memory inter-
face. It enables better system performance especially when 2 or 3 wait state needed.
For systems requiring only 1 wait state, or to privilege current consumption rather than perfor-
mance, the user can select a 64-bit wide memory access via the FAM bit in the Flash Mode
Register (EEFC_FMR)
Please refer to the electrical characteristics section of the product datasheet for more details.
A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential Code Fetch.
Note:
@Byte 4
Bytes 0-3
XXX
Immediate consecutive code read accesses are not mandatory to benefit from this optimization.
Bytes 16-31
@Byte 8
Bytes 4-7
@Byte 12
Bytes 8-11
Bytes 0-15
@Byte 16
Bytes 12-15
Bytes 32-47
@Byte 20
Bytes 16-19
Bytes 16-31
@Byte 24
Bytes 20-23
SAM3U Series
SAM3U Series
Bytes 24-27
@Byte 28
Bytes 32-47
@Byte 32
Bytes 28-31
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