SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 818

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Note:
37.8.2
37.8.3
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818
1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed MultiMe-
SAM3U Series
SAM3U Series
Data Transfer Operation
Read Operation
dia Card specification).
The High Speed MultiMedia Card allows several read/write operations (single block, multiple
blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP)
field in the HSMCI Command Register (HSMCI_CMDR).
These operations can be done using the features of the DMA Controller.
In all cases, the block length (BLKLEN field) must be defined either in the mode register
HSMCI_MR, or in the Block Register HSMCI_BLKR. This field determines the size of the data
block.
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
The following flowchart
DMAC facilities. In this example, a polling method is used to wait for the end of read. Similarly,
the user can configure the interrupt enable register (HSMCI_IER) to trigger an interrupt at the
end of read.
• Open-ended/Infinite Multiple block read (or write):
• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The number of blocks for the read (or write) multiple block operation is not defined. The card
will continuously transfer (or program) data blocks until a stop transmission command is
received.
The card will transfer (or program) the requested number of data blocks and terminate the
transaction. The stop command is not required at the end of this type of multiple block read
(or write), unless terminated with an error. In order to start a multiple block read (or write)
with pre-defined block count, the host must correctly program the HSMCI Block Register
(HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT
field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks).
Programming the value 0 in the BCNT field corresponds to an infinite block transfer.
(Figure
37-8) shows how to read a single block with or without use of
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11