SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 178

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.20 System control block
Table 13-30. Summary of the system control block registers
Notes:
13.20.1
178
Address
0xE000E008
0xE000ED00
0xE000ED04
0xE000ED08
0xE000ED0C
0xE000ED10
0xE000ED14
0xE000ED18
0xE000ED1C
0xE000ED20
0xE000ED24
0xE000ED28
0xE000ED28
0xE000ED29
0xE000ED2A
0xE000ED2C
0xE000ED34
0xE000ED38
0xE000ED3C
1. See the register description for more information.
2. A subregister of the CFSR.
SAM3U Series
The CMSIS mapping of the Cortex-M3 SCB registers
Name
ACTLR
CPUID
ICSR
VTOR
AIRCR
SCR
CCR
SHPR1
SHPR2
SHPR3
SHCRS
CFSR
MMSR
BFSR
UFSR
HFSR
MMAR
BFAR
AFSR
(2)
(2)
(2)
The System control block (SCB) provides system implementation information, and system con-
trol. This includes configuration, control, and reporting of the system exceptions. The system
control block registers are:
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the byte array SHP[0] to SHP[12] corresponds to the registers SHPR1-SHPR3.
Type
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(1)
(1)
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Reset
value
0x00000000
0x412FC230
0x00000000
0x00000000
0xFA050000
0x00000000
0x00000200
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00
0x00
0x0000
0x00000000
Unknown
0x00000000
Unknown
Description
“Auxiliary Control Register” on page 179
“CPUID Base Register” on page 180
“Interrupt Control and State Register” on page 181
“Vector Table Offset Register” on page 184
“Application Interrupt and Reset Control Register” on page
185
“System Control Register” on page 187
“Configuration and Control Register” on page 188
“System Handler Priority Register 1” on page 191
“System Handler Priority Register 2” on page 192
“System Handler Priority Register 3” on page 192
“System Handler Control and State Register” on page 193
“Configurable Fault Status Register” on page 195
“Memory Management Fault Address Register” on page
202
“Bus Fault Status Register” on page 197
“Usage Fault Status Register” on page 199
“Hard Fault Status Register” on page 201
“Memory Management Fault Address Register” on page
202
“Bus Fault Address Register” on page 203
“Auxiliary Fault Status Register” on page 204
6430E–ATARM–29-Aug-11