SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 970

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 39-13. Data OUT Transfer for Endpoint with One Bank
970
970
USB Bus
Packets
RX_BK_RDY
(UDPHS_EPTSTAx)
FIFO (DPR)
Content
SAM3U Series
SAM3U Series
Token OUT
Host Sends Data Payload
Written by UDPHS Device
See
information.
DMA Configuration Example:
For OUT transfer, the bank will be automatically cleared by hardware when the application has
read all the bytes in the bank (the bank is empty).
Notes:
Data OUT 1
Data OUT 1
1. First program UDPHS_DMAADDRESSx with the address of the buffer that should be
2. Enable the interrupt of the DMA in UDPHS_IEN
3. Program the DMA Channelx Control Register:
39.6.9.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
transferred.
– Size of buffer to be sent.
– END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered
– END_BUFFIT: Generate an interrupt when BUFF_COUNT in the
– END_TR_EN: End of transfer enable, the UDPHS device can put an end to the
– END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB
– CHANN_ENB: Run and stop at end of buffer.
packet data) at the end of DMA buffer.
UDPHS_DMASTATUSx register reaches 0.
current DMA transfer, in case of a short packet.
packet has been transferred by the DMA, if the USB transfer ended with a short
packet. (Beneficial when the receive size is unknown.)
1. When a zero-length-packet is received, RX_BK_RDY bit in UDPHS_EPTSTAx is cleared auto-
2. If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK.
matically by AUTO_VALID, and the application knows of the end of buffer by the presence of
the END_TR_IT.
No data is written in the endpoint, the RX_BY_RDY interrupt is generated, and the
BYTE_COUNT field in UDPHS_EPTSTAx is null.
Host Sends the Next Data Payload
ACK
Microcontroller Read
Set by Hardware
Microcontroller Transfers Data
Data OUT 1
Token OUT
Interrupt Pending
Data OUT 2
NAK
Cleared by Firmware,
Data Payload Written in FIFO
Token OUT
Host Resends the Next Data Payload
Written by UDPHS Device
Data OUT 2
Data OUT 2
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
for more
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