ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 127

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.7
12.8
12.8.1
12.8.2
8077H–AVR–12/09
Moving Interrupts Between Application and Boot Section
Register Description
STATUS - PMIC Status Register
INTPRI - PMIC Priority Register
The interrupt vectors can be moved from the default location in the Application Section in Flash
to the start of the Boot Section.
• Bit 7 - NMIEX: Non-Maskable Interrupt Executing
This flag is set if a Non-Maskable Interrupt is executing. The flag will be cleared when returning
(RETI) from the interrupt handler.
• Bit 6:3 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2 - HILVLEX: High Level Interrupt Executing
This flag is set if a high level interrupt is executing or the interrupt handler has been interrupted
by an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
• Bit 1 - MEDLVLEX: Medium Level Interrupt Executing
This flag is set if a medium level interrupt is executing or the interrupt handler has been inter-
rupted by an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI)
from the interrupt handler.
• Bit 0 - LOLVLEX: Low Level Interrupt Executing
This flag is set if a low level interrupt is executing or the interrupt handler has been interrupted by
an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the
interrupt handler.
• Bit 7:0 - INTPRI: Interrupt Priority
When round-robin scheduling is enabled, this register stores the interrupt vector of the last
acknowledged low-level interrupt. The stored interrupt vector will have the lowest priority next
time one or more low-level interrupts are pending. The register is accessible from software to
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
NMIEX
R/W
R
7
0
7
0
R/W
R
6
0
6
0
-
R/W
R
5
0
-
5
0
R/W
R
4
0
-
4
0
INTPRI[7:0]
R/W
R
3
0
-
3
0
HILVLEX
R/W
R
2
0
2
0
MEDLVLEX
R/W
R
1
0
1
0
XMEGA A
LOLVLEX
R/W
R
0
0
0
0
STATUS
INTPRI
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