ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 93

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.11.4
7.11.5
7.11.6
7.11.6.1
8077H–AVR–12/09
COMP0 - Oscillator Compare Register 0
COMP1 - Oscillator Compare Register 1
COMP2 - Oscillator Compare Register 2
COMP2 - Oscillator Compare Register 2, 2 MHz DFLL /32 MHz DFLL
• Bit 4:0 - CALH[12:8]: DFLL Calibration bits
These bits hold the 6 Most Significant Bits (MSB) of the calibration value for the oscillator. A fac-
tory-calibrated value is loaded from the signature row of the device and written to this register
during reset, giving an oscillator frequency approximate to the nominal frequency for the oscilla-
tor. These bits are not changed during automatic runtime calibration of the oscillator.
COMP0, COMP1 and COMP2 represent the register value COMP that hold the oscillator com-
pare value. During reset COMP is loaded with the default value representing the ideal
relationship between oscillator frequency and the 1.024 kHz reference clock. It is possible to
write these bits from software, and then enable the oscillator to tune to a frequency different than
its nominal frequency. These bits can only be written when the DFLL is disabled.
• Bit 7:0 - COMP[7:0]
These bits are the low byte of the COMP register.
• Bit 7:0 - COMP[15:8]
These bits are the middle byte of the COMP register.
• Bit 7:0 - COMP[23:16]
These bits are the highest bits of the COMP register.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
COMP[23:16]
COMP[15:8]
COMP[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
0
0
0
0
0
0
COMP1
COMP2
COMP0
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