ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 286

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ATAVRDISPLAYX

Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Datasheets

Specifications of ATAVRDISPLAYX

Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
24.12.3
24.12.4
8077H–AVR–12/09
CTRLB (SDRAM) - Chip Select Control Register B
BASEADDR - Chip Select Base Address Register
Table 24-19. Wait State selection (Continued)
This configuration options in this register depend on the Chip Select Mode configuration. The
register description below is valid when the Chip Select Mode is configured for SDRAM
• Bit 7 - SDINITDONE: SDRAM Initialization Complete
This flag is set at the end of the SDRAM initialization sequence. The flag will remain set as long
as the EBI is enabled and the Chip Select is configured for SDRAM.
• Bit 6:3 - Reserved
These bits are reserved and will always be read as zero.
• Bit 2 - SDSREN: SDRAM Self-refresh Enable
When this bit is written to one the EBI controller will send a Self-refresh command to the
SDRAM. For leaving the self refresh mode, the bit must be written to zero.
• Bit 1:0 SDMODE[1:0]: SDRAM Mode
These bits select mode when accessing the SDRAM according to
Table 24-20. SDRAM Mode
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
+0x03
Read/Write
Initial Value
SRMODE[1:0]
SRWS[2:0]
00
01
10
11
101
110
111
SDINITDONE
R/W
R/W
15
7
0
0
R/W
7
0
NORMAL
LOAD
-
-
Group Configuration
BASEADDR[15:12]
R/W
R/W
14
6
0
0
Group Configuration
5CLK
6CLK
7CLK
R/W
6
0
-
R/W
R/W
13
5
0
0
R/W
5
0
-
BASEADDR[23:16]
R/W
R/W
12
4
0
0
Normal Mode. Access to the SDRAM is decoded normally.
Load Mode. The EBI issues a “Load Mode Register”
command when the SDRAM is accessed.
Reserved
Reserved
Description
R/W
4
0
-
Description
5 CLK
6 CLK
7 CLK
R/W
R/W
11
3
0
0
-
PER2
PER2
PER2
R/W
3
0
-
cycles wait state
cycles wait state
cycles wait state
R/W
R/W
10
2
0
0
-
SDREN
R/W
2
0
Table 24-20 on page
R/W
R/W
1
9
0
0
-
R/W
SDMODE[1:0]
1
0
R/W
R/W
0
8
0
0
-
XMEGA A
R/W
0
0
BASEADDRL
BASEADDRH
.
CTRLB
286.
286

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