ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 253

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8077H–AVR–12/09
• Bits 5:4 - PMODE[1:0]: Parity Mode
These bits enable and set the type of parity generation according to
When enabled, the Transmitter will automatically generate and send the parity of the transmitted
data bits within each frame. The Receiver will generate a parity value for the incoming data and
compare it to the PMODE setting and if a mismatch is detected, the PERR flag in STATUS will
be set.
These bits are unused in Master SPI mode of operation.
Table 21-7.
• Bit 3 - SBMODE: Stop Bit Mode
This bit selects the number of stop bits to be inserted by the Transmitter according to
on page
This bit is unused in Master SPI mode of operation.
Table 21-8.
• Bit 2:0 - CHSIZE[2:0]: Character Size
The CHSIZE[2:0] bits sets the number of data bits in a frame according to
253. The Receiver and Transmitter use the same setting.
Table 21-9.
PMODE[1:0]
CHSIZE[2:0]
2. See
253. The Receiver ignores this setting.
000
001
010
011
100
101
110
111
00
01
10
11
PMODE Bits Settings
SBMODE Bit Settings
CHSIZE Bits Settings
”USART” on page 235
SBMODE
0
1
Group Configuration
Group Configuration
DISABLED
EVEN
ODD
5BIT
6BIT
7BIT
8BIT
9BIT
for full description of the Master SPI Mode (MSPIM) operation.
Parity mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Character size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
Stop Bit(s)
1-bit
2-bit
Table 21-7 on page
Table 21-9 on page
XMEGA A
Table 21-8
253.
253