ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 232

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.6
20.7
20.7.1
8077H–AVR–12/09
DMA Support
Register Description
CTRL - SPI Control Register
DMA support on the SPI module is only available in Slave mode. The SPI Slave can trigger a
DMA transfer as one byte has been shifted into the Data Register. It is possible to set up the
XMEGA USART in SPI mode to have DMA support for master mode, for details refer to
21.10 ”USART in Master SPI Mode” on page
• Bit 7 - CLK2X: SPI Clock Double
When this bit is set the SPI speed (SCK Frequency) will be doubled in Master mode (see
20-4 on page
• Bit 6 - ENABLE: SPI Enable
Setting this bit enables the SPI modules. This bit must be set to enable any SPI operations.
• Bit 5 - DORD: Data Order
DORD decide the data order when a byte is shifted out from the Data register. When DORD is
written to one, the LSB of the data byte is transmitted first, and when DORD is written to zero,
the MSB of the data byte is transmitted first.
• Bit 4 - MASTER: Master/Slave Select
This bit selects Master mode when written to one, and Slave mode when written to zero. If SS is
configured as an input and is driven low while MASTER is set, MASTER will be cleared.
• Bit 3:2 - MODE[1:0]: SPI Mode
These bits select the transfer mode. The four combinations of SCK phase and polarity with
respect to serial data is shown in
a clock cycles (leading edge) is rising or falling, and if data setup and sample is on lading or trail-
ing edge.
When the leading edge is rising the bit SCK is low when idle, and when the leading edge is fall-
ing the SCK is high when idle.
Table 20-3.
Bit
+0x00
Read/Write
Initial Value
MODE[1:0]
00
01
10
11
CLK2X
R/W
233).
7
0
SPI transfer modes
ENABLE
Group Configuration
R/W
6
0
0
1
2
3
DORD
R/W
5
0
Figure 20-3 on page
MASTER
R/W
4
0
247.
Rising, Sample
Leading Edge
Falling,Sample
Rising, Setup
Falling, Setup
R/W
3
0
MODE[1:0]
232. This decide whether the first edge in
R/W
2
0
R/W
PRESCALER[1:0]
1
0
Falling, Sample
Rising, Sample
Trailing Edge
Falling, Setup
Rising, Setup
XMEGA A
R/W
0
0
Section
CTRL
Table
232