ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 80

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
Figure 7-5.
8077H–AVR–12/09
External Oscillator or Clock.
Internal 32.768 kHz Osc.
Internal 32 MHz Osc.
Internal 2 MHz Osc.
System Clock Selection and Prescalers
Internal PLL.
System Clock Selection and Prescalers
Clock Selection
7-4 on page
oscillator can be used as clock source for the System Clock, RTC and as the DFLL reference.
Figure 7-4.
Two capacitors, C1 and C2, may be added to match the required load capacitance for the con-
nected crystal.
All the calibrated internal oscillators, the external clock sources (XOSC) and the PLL output can
be used as the System Clock source. The System Clock source is selectable from software, and
can be changed during normal operation. Built-in hardware protection prevents unsafe clock
switching. It is not possible to select a non-stable or disabled oscillator as clock source, or to dis-
able the oscillator currently used as system clock source. Each oscillator option has a status flag
that can be read from software to check that the oscillator is ready.
The System Clock is fed into a prescaler block that can divide the clock signal by a factor from 1
to 2048 before it is routed to the CPU and peripherals. The prescaler settings can be changed
from software during normal operation. The first stage, prescaler A, can divide by a factor of 1 to
512. Then prescaler B and C can be individually configured to either pass the clock through or
divide it by a factor of 1 to 4. The prescaler guarantees that derived clocks are always in phase,
and that no glitches or intermediate frequencies occur when changing the prescaler setting. The
prescaler settings are always updated in accordance to the rising edge of the slowest clock.
Prescaler A divides the System Clock and the resulting clock is the clk
prescaler C can be enabled to divide the clock speed further and enable peripheral modules to
run at twice or four times the CPU Clock frequency. If Prescaler B and C are not used all the
clocks will run at the same frequency as output from Prescaler A.
Clk
SYS
1, 2, 4, ... , 512
Prescaler A
80. A low power mode with reduced voltage swing on TOSC2 is available. This
32.768 kHz crystal oscillator connection
Clk
Prescaler B
PER4
1, 2, 4
C 2
C 1
Clk
Prescaler C
PER2
1, 2
T O S C 2
T O S C 1
G N D
Clk
Clk
CPU
PER
PER4
XMEGA A
. Prescaler B and
80