ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 321

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.10.3
8077H–AVR–12/09
CTRLC – DAC Control Register C
Table 26-1.
• Bits 4:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 - CH1TRIG: DAC Auto trigged mode Channel 1
If this bit is set, the incoming event on the event channel selected in the EVCTRL Register will
start the conversion when a new value is written to high byte of the data register CH1DATA.
• Bit 0 - CH0TRIG: DAC Auto trigged mode Channel 0
If this bit is set, the incoming event on the event channel selected in the EVCTRL Register will
start the conversion when a new value is written to high byte of the data register CH0DATA.
• Bits 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 4:3 - REFSEL[1:0]: DAC Reference Selection
These bits control the reference and thus the conversion range of the DAC.
Table 26-2
Table 26-2.
• Bit 2:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x02
Read/Write
Initial Value
CHSEL[1:0]
REFSEL[1:0]
00
01
10
11
00
01
10
11
shows the available options.
R
7
0
-
DAC channel selection
DAC Reference selection
Description
Single channel operation (for channel 0 only)
Reserved
Duel channel operation (S/H for channel 0 and channel 1)
Reserved
R
6
0
-
Group Configuration
AREFB
AREFA
R
INT1V
5
0
AVCC
-
R/W
4
0
REFSEL[1:0]
R/W
3
0
R/W
2
0
-
AREF on PORTB
AREF on PORTA
Internal 1.00 V
Description
AV
R/W
1
0
-
CC
XMEGA A
LEFTADJ
R/W
0
0
CTRLC
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