ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 206

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3
8077H–AVR–12/09
General TWI Bus Concepts
It is possible to disable the internal TWI drivers in the device, and enabling a 4-wire interface for
connecting external bus drivers.
The Two-Wire Interface (TWI) provides a simple two-wire bi-directional bus consisting of a serial
clock line (SCL) and a serial data line (SDA). The two lines are open collector lines (wired-AND),
and pull-up resistors (Rp) are the only external components needed to drive the bus. The pull-up
resistors will provide a high level on the lines when none of the connected devices are driving
the bus. A constant current source can be used as an alternative to the pull-up resistors.
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus.
A device connected to the bus can be a master or slave, where the master controls the bus and
all communication.
Figure 19-1
Figure 19-1. TWI Bus Topology
A unique address is assigned to all slave devices connected to the bus, and the master will use
this to address a slave and initiate a data transaction. 7-bit or 10-bit addressing can be used.
Several masters can be connected to the same bus, and this is called a multi-master environ-
ment. An arbitration mechanism is provided for resolving bus ownership between masters since
only one master device may own the bus at any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by
responding to more than one address.
A master indicates the start of transaction by issuing a START condition (S) on the bus. An
address packet with a slave address (ADDRESS) and an indication whether the master wishes
to read or write data (R/W), is then sent. After all data packets (DATA) are transferred, the mas-
ter issues a STOP condition (P) on the bus to end the transaction. The receiver must
acknowledge (A) or not-acknowledge (A) each byte received.
Figure 19-2
SDA
SCL
V
CC
illustrates the TWI bus topology.
shows a TWI transaction.
R
P
R
P
DEVICE #1
TWI
R
S
R
S
DEVICE #2
TWI
R
S
R
S
XMEGA A
Note: R
DEVICE #N
TWI
R
S
S
is optional
R
S
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