ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 6
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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8077H–AVR–12/09
Figure 3-1.
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or
between a constant and a register. Single register operations can also be executed in the ALU.
After an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
The ALU is directly connected to the fast-access Register File. The 32 x 8-bit general purpose
working registers all have single clock cycle access time allowing single-cycle Arithmetic Logic
Unit (ALU) operation between registers or between a register and an immediate. Six of the 32
registers can be used as three 16-bit address pointers for program and data space addressing -
enabling efficient address calculations.
The memory spaces are all linear and regular memory maps. The Data Memory space and the
Program Memory space are two different memory spaces.
The Data Memory space is divided into I/O registers and SRAM. In addition the EEPROM can
be memory mapped in the Data Memory.
All I/O status and control registers reside in the lowest 4K bytes addresses of the Data Memory.
This is referred to as the I/O Memory space. The lowest 64 addresses can be accessed directly,
or as the data space locations from 0x00 - 0x3F. The rest is the Extended I/O Memory space,
ranging from 0x40 to 0x1FFF. I/O registers here must be access as data space locations using
load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
Peripheral
Module 1
Block Diagram of the AVR Architecture
CONTROL
STATUS/
Program
Counter
OCD
Peripheral
Module n
Instruction
Instruction
Program
Register
Memory
Decode
Flash
DATA BUS
SRAM
DATA BUS
ALU
EEPROM
32 x 8 General
Registers
Multiplier/
Purpose
DES
PMIC
XMEGA A
6
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