ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 211

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.9
8077H–AVR–12/09
Synchronization
Figure 19-9. TWI Arbitration
Figure 19-9
devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to
transmit a high level (bit 5) while DEVICE2 is transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data
bit, or a repeated START condition and STOP condition are not allowed and will require special
handling by software.
A clock synchronization algorithm is necessary for solving situations where more than one mas-
ter is trying to control the SCL line at the same time. The algorithm is based on the same
principles used for clock stretching previously described.
two masters are competing for the control over the bus clock. The SCL line is the wired-AND
result of the two masters clock outputs.
Figure 19-10. Clock Synchronization
A high to low transition on the SCL line will force the line low for all masters on the bus and they
start timing their low clock period. The timing length of the low clock period can vary between the
masters. When a master (DEVICE1 in this case) has completed its low period it releases the
SCL line. However, the SCL line will not go high before all masters have released it. Conse-
quently the SCL line will be held low by the device with the longest low period (DEVICE2).
Devices with shorter low periods must insert a wait-state until the clock is released. All masters
start their high period when the SCL line is released by all devices and has become high. The
DEVICE1_SCL
DEVICE2_SCL
SCL
(wired-AND)
DEVICE1_SDA
DEVICE2_SDA
SDA
(wired-AND)
SCL
shows an example where two TWI masters are contending for bus ownership. Both
S
Low Period
Count
DEVICE1 Loses arbitration
bit 7
State
Wait
Figure 19-10
bit 6
High Period
Count
bit 5
shows an example where
XMEGA A
bit 4
211