ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 239

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.4
21.3.5
8077H–AVR–12/09
Synchronous Clock Operation
SPI Clock Generation
When synchronous mode is used, the XCK pin controls whether the transmission clock is input
(slave mode) or output (master mode). The corresponding port pin must be set to output for
master mode and to input for slave mode. The normal port operation of the XCK pin will be over-
ridden. The dependency between the clock edges and data sampling or data change is the
same. Data input (on RxD) is sampled at the opposite XCK clock edge of the edge where data
output (TxD) is changed.
Figure 21-3. Synchronous Mode XCKn Timing.
Using the Inverted I/O (INVEN) setting in the Pin Configuration Register for the corresponding
XCK port pin, it is selectable which XCK clock edge is used for data sampling and which is used
for data change. If inverted I/O is disabled (INVEN=0) data will be changed at rising XCK clock
edge and sampled at falling XCK clock edge. If inverted I/O is enabled (INVEN=1) data will be
changed at falling XCK clock edge and sampled at rising XCK clock edge. For more details, see
in “I/O Ports” on page 106.
For SPI operation only master mode with internal clock generation is supported. This is identical
to the USART synchronous master mode and the baud rate or BSEL setting are calculated by
using the same equations, see
There are four combinations of the XCK (SCK) clock phase and polarity with respect to serial
data, and these are determined by the Clock Phase (UCPHA) control bit and the Inverted I/O pin
(INVEN) setting. The data transfer timing diagrams are shown in
bits are shifted out and latched in on opposite edges of the XCK signal, ensuring sufficient time
for data signals to stabilize. The UCPHA and INVEN settings are summarized in
page
Receiver and Transmitter.
Table 21-2.
SPI Mode
239. Changing the setting of any of these bits during transmission will corrupt for both the
0
1
2
3
INVEN and UCPHA Functionality
INVEN = 1
INVEN = 0
INVEN
0
0
1
1
RxD / TxD
RxD / TxD
XCK
XCK
Table 21-1 on page
UCPHA
0
1
0
1
Leading Edge
Rising, Sample
Rising, Setup
Falling, Sample
Falling, Setup
238.
Figure 21-4 on page
Sample
Sample
Trailing Edge
Falling, Setup
Falling, Sample
Rising, Setup
Rising, Sample
XMEGA A
Table 21-2 on
240. Data
239