ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 148

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.17 Register Summary – Ports
13.18 Register Summary – Port Configuration
13.19 Register Summary – Virtual Ports
13.20 Interrupt vector Summary - Ports
Table 13-9.
8077H–AVR–12/09
Address
Address
Address
+0x0A
+0x0B
+0x0C
+0x0D
+0x0E
+0x1A
+0x1B
+0x1C
+0x1D
+0x1E
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x08
+0x09
+0x0F
+0x10
+0x11
+0x12
+0x13
+0x14
+0x15
+0x16
+0x17
+0x18
+0x19
+0x1F
+0x00
+0x01
+0x02
+0x03
+0x04
+0x00
+0x01
+0x02
+0x03
Offset
0x00
0x02
Name
Name
Name
Ports Interrupt vectors and their word offset address
CLKEVOUT
INT0MASK
INT1MASK
MPCMASK
INTFLAGS
PIN0CTRL
PIN1CTRL
PIN2CTRL
PIN3CTRL
PIN4CTRL
PIN5CTRL
PIN6CTRL
PIN7CTRL
INTFLAGS
VPCTRLA
VPCTRLB
INTCTRL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OUTSET
OUTCLR
OUTTGL
DIRSET
DIRCLR
DIRTGL
OUT
OUT
DIR
DIR
IN
IN
INT0_vect
INT1_vect
Source
SRLEN
SRLEN
SRLEN
SRLEN
SRLEN
SRLEN
SRLEN
SRLEN
Bit 7
Bit 7
Bit 7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
Bit 6
Bit 6
Bit 6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VP1MAP[3:0]
VP3MAP[3:0]
Interrupt Description
Port Interrupt vector 0 offset
Port Interrupt vector 1 offset
Bit 5
Bit 5
Bit 5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVOUT[1:0]
OPC[2:0]
OPC[2:0]
OPC[2:0]
OPC[2:0]
OPC[2:0]
OPC[2:0]
OPC[2:0]
OPC[2:0]
Bit 4
Bit 4
Bit 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MPCMASK[7:0]
INT0MSK[7:0]
INT1MSK[7:0]
OUTSET[7:0]
OUTCLR[7:0]
OUTTGL[7:0]
DIRSET[7:0]
DIRCLR[7:0]
DIRTGL[7:0]
OUT[7:0]
OUT[7:0]
DIR[7:0]
DIR[7:0]
IN[7:0]
IN[7:0]
Bit 3
Bit 3
Bit 3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INT1LVL[1:0]
Bit 2
Bit 2
Bit 2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VP0MAP[3:0]
VP2MAP[3:0]
INT1IF
INT1IF
Bit 1
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
Bit 1
Bit 1
-
-
-
-
-
-
-
-
-
-
-
-
CLKOUT[1:0]
INT0LVL[1:0]
XMEGA A
Bit 0
INT0IF
Bit 0
Bit 0
INT0IF
-
-
-
-
-
-
-
-
-
-
-
-
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